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context switching |
Also found in: Wikipedia | 0.11 sec. |
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Same as task switching. |
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? Mentioned in | ? References in periodicals archive | ||
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| They lack this capability primarily because of their memory management schemes, context switching overhead and the lack of special function units that are necessary for protocol processing. The new RTOS, which now supports PowerPC, ARM, MIPS, and XScale processors, features full memory protection and guaranteed resource availability, yet still delivers sub-200-nsec interrupt response and sub-microsecond context switching (as measured on a 233-MHz processor). Occupying less than 8 kbytes of memory (in a minimal configuration), OSEck delivers fully-preemptive, event-driven real-time response with a context switching speed of 150 nsec and a worst-case interrupt latency of 300 nsec (assuming 850-MHz clock frequency). |
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