cycle stealing


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cycle stealing

[′sī·kəl ‚stēl·iŋ]
(computer science)
A technique for memory sharing whereby a memory may serve two autonomous masters, commonly a central processing unit and an input-output channel or device controller, and in effect provide service to each simultaneously.

cycle stealing

A CPU design technique that periodically "grabs" machine cycles from the main processor usually by some peripheral control unit, such as a DMA (direct memory access) device. In this way, processing and peripheral operations can be performed concurrently or with some degree of overlap. See also peer-to-peer computing.
References in periodicals archive ?
Police in Hereford have launched a new campaign against thieves who are responsible for a cycle stealing spree.
The tool's flexibility supports a wide variety of design styles, including multiple clocks (both edge-triggered and level-sensitive) with cycle stealing.
The Fujitsu SPARClite ISS model will support all major functional capabilities of the SPARClite processor, including cache hits/misses for instruction and data cache, cycle counts, burst mode, write buffer, pre- fetch, and cycle stealing.