data bus


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data bus

[′dad·ə ‚bəs]
(electronics)
An internal channel that carries data between a computer's central processing unit and its random-access memory.

data bus

(architecture)
The bus (connections between and within the CPU, memory, and peripherals) used to carry data. Other connections are the address bus and control signals.

The width and clock rate of the data bus determine its data rate (the number of bytes per second it can carry), which is one of the main factors determining the processing power of a computer. Most current processor designs use a 32-bit bus, meaning that 32 bits of data can be transferred at once. Some processors have an internal data bus which is wider than their external bus in order to make external connections cheaper while retaining some of the benefits in processing power of a wider bus.

See also data path.

data bus

An internal pathway across which data are transferred to and from the processor or to and from memory. See local bus, system bus and peripheral bus.
References in periodicals archive ?
The Ultra160 uses a SPI-3 third generation parallel SCSI interface, which adds five new features: (1) Fast-80 or a data bus speed running at 80 MHz; (2) Cyclic Redundancy Check (CRC)--a common error checking protocol, which is used to ensure data integrity as a safety measure since transfer speeds were being increased, leading to the possibility of data corruption; (3) Domain Validation, which improves the robustness of the process by which different SCSI devices determine an optimal data transfer rate; (4) Quick arbitration and selection (QAS), which represents a change in the way devices determine which device has control of the SCSI bus.
The problem comes from multiple disc drives sharing the available data bus bandwidth, which limits the throughput and can slow transaction on intensive applications.
The contract is to design, configure, implement ZSRK integration with SAP PI data bus for data transmitted by a computer system (MS-NW WF) in the Ministry of Justice on the data bus.
The addition of the triple data bus in a nine-layer MCP further demonstrates Toshiba's advanced packaging leadership and enables us to optimize overall performance of the memory subsystem, while giving our customers the flexibility to choose the type and density of memory they need to meet the requirements of today's and tomorrow's advanced multimedia- equipped cellular phones," said Scott Beekman, business development manager, communication memory products, for TAEC.
Bus Design: The latest revision of the ATA specification, ATA/ATAPI-6 where Ultra ATA 100 is defined, maintains backward compatibility with all previous ATA revisions, using the standard 16-bit, wide, parallel data bus and 16 control signals across a 40-pin connector.
The VMC-SmartDisplay[TM] will combine Planar's EL display technology, which has more than 25 years of proven durability in harsh conditions, with embedded software and a microprocessor to interface with a vehicle's data bus and analog sensors.
Information will be provided on the many ways to connect compact disc-read only memory (CD-ROM) to a desktop or laptop personal computer (PC), key decisions to be made before purchasing a CD-ROM drive, and the type of monitor, speakers and data bus needed.
This Data Bus Market report provides a detailed analysis and forecast for the commercial & military aviation and automotive industries with a market analysis of the data bus market, over the next six years.
API Technologies Corporation declared that it has agreed to sell its Data Bus product line to Data Device Corporation (DDC) in a cash deal for $32.
According to the new market research report " Data Bus Market by Protocol (MIL-STD, AFDX, ARINC 429/629, CAN, TTP), by Application (Military, Commercial Aviation, Automotive), by Component (Micro couplers, Cables, Connectors, Accessories), by Geography - Global Forecasts & Analysis to 2020" , published by MarketsandMarkets, the global Data Bus Market is expected to reach $8.
Both ONFI and Toggle versions support single-channel operations in x8 and x16 data bus widths, and dual- and quad-channel operations in x8 bit data bus width, which allows operations of up to 400 million transactions per second.
The devices conform to the SigmaRAM Consortium's Sigma 1x1Dp double-late-write, pipeline-read specification, which enables 100 percent data bus efficiency and avoids data bus collision even in read/write alternate operation.