delay element

delay element

[di′lā ‚el·ə·mənt]
(ordnance)
A component which provides a specified delay between actuation of the propellant-actuated devices and ignition of the propellant.
References in periodicals archive ?
If the modifier is a [DELTA][PHI] phase delay element, then the PLL inputs will be [DELTA][PHI] delayed from the output, so the output will be 360[degrees]- [DELTA][ohm] delayed from the input.
The DLL (Delay Locked Loop, on-chip device) is a fixed or adjustable delay element.
Milking lets the striker hit the primer, which initiates the fuze delay element without the thrower being aware the fuse is burning.
The detonator itself is a metal tube, usually aluminum, containing a delay element and explosives.
Interleaving is possible to easily choose simple settings such as symbol width, number of branches, and unit delay element.
Replacing each delay elements of both filters by M delays, two filters with transfer functions [H.
Anisochronic systems and models (Bellmann & Cooke, 1963; Hale & Lunel, 1993; Zitek & Vitecek, 1999), on the other hand, offer a more universal dynamics description applying delay elements on the left-hand side of a differential equation, which reflects a natural feature of many processes that they own delays in internal feedback loops (i.
The Master delay hardmacro measures parts of the clock period using precise analog delay elements and provides a 90-degree delay over PVT.
Integrating detection, assessment, and delay elements into a protective system requires a logical, systematic approach.
In addition, Hammer 100 now supports delay elements, to facilitate designs using intellectual property or legacy blocks as is.
The built-in DQS phase shift circuitry found only in Altera's industry-leading FPGAs is the optimal phase shift solution and eliminates the need to use less efficient design techniques such as varying signal trace lengths or adding fixed delay elements, which dramatically complicate board design.
The interconnects automatically ensure the proper alignment of data prior to performing bit-error-rate (BER) simulations without the need for delay elements for each block.