It allows abstracting away the need to serialize and deserialize
request and response messages manually.
The circuits used in JBODs and hubs differ substantially from SerDes since, for the most part, these systems do not deserialize
data, but rather route serial data within the system.
The receiver's high input-jitter tolerance guarantees the deserializer will successfully receive, lock and deserialize
incoming video streams that have accumulated noise, even with up to 70 percent of the signal's eye closed.
Part of the High Speed Logic family of devices, the 1385DX, with its high sensitivity latched comparator input and auto-synchronizing demultiplexer, enables test and measurement, defense, and aerospace designers to develop high speed data acquisition front ends and to deserialize
high speed signals.
6 unit intervals (UI), allowing the product to receive and deserialize
signals with more than 60 percent of the signal's "eye" closed.
The Tektronix TMS817 is used to deserialize
, descramble, deskew and decode the PCI Express data stream into the proper transactions so that customers can use the TLA700 to debug and validate PCI Express from a system level.
SerDes ICs serialize and deserialize
low-speed parallel interfaces to high-speed serial connections.
Along with the FPGA development board, a separate FMC daughter card deserializes
the data from the four cameras.
The decoding function is just the opposite of the encoding one, meaning the Codec receives a TriMessage from the Adapter, containing the QED Response, deserializes
it, converts it into a Java structure and forwards it to the TE.
The companion VSC8132 Demultiplexer deserializes
The new reference design, together with the accompanying application note, deserializes
data streams from TI's ADS6000 analog-to-digital converter (ADC) family, providing designers a quick and easy solution with which to deploy products based on the latest advanced ADC device technology.
This new reference design, which deserializes
bit streams from TI's ADS527x analog-to- digital converter (ADC) family, and accompanying application note provide a quick and easy solution for designers to integrate a serial, high-speed LVDS receiver into the Xilinx(R) Virtex-II(TM) series, Virtex-II Pro(TM) and Spartan-3(TM) FPGAs.