Intel offers a true die shrink
with its second-generation 14 nm Tri-Gate process, relative to alternative FinFET technologies.
The die shrink
will offer backward compatibility and performance enhancement, while achieving the common targets shared with customers on cost control," said Martin Lin, Segment Marketing Director at Macronix.
It's functionally the same ASIC [as the Bloom I] but we've done a die shrink
," said Brocade's marketing vice president Jay Kidd.
has led to cost reductions; TriQuint pioneered in this area," said Balut.
The Mali55 is a die shrink
of the Mali110, allowing for advanced multimedia capabilities for the value market.
As well, this analysis reveals that the 970FX delivers a 50% die shrink
(to 65mm2) over its 130nm predecessor, including the 6-T SRAM cell size.
The die shrink
can also lead to much higher-performing devices," said Dan Hutcheson, president and CEO at VLSI Research Inc.
The lower density was achieved through a die shrink
- which allowed use of a smaller 44-pin QFP with tighter lead spacing.
50 Percent Die Shrink
Increases Production, Clock Speeds
Pad pitch reduction in the bonding process is especially critical in meeting today's die shrink
challenges, an important component in lowering costs in semiconductor manufacturing.
Creating interconnect on top of the die placed in a reconstituted wafer format permitted a package structure that could handle higher I/Os, as the move to advanced silicon technology nodes provided die shrinks
However, the company believes the industry went through a paradigm shift during the past recession, moving to more aggressive die shrinks
and to 300 mm processing to increase production.