The System for Differential Corrections
and Monitoring (SDCM) is the Satellite-based augmentation system (SBAS) currently being developed in the Russian Federation as a component of GLONASS.
Using internal and external receivers (antenna located within the receiver--internal, antenna attached externally to receiver--external), the studies experimented with WAAS and postprocess differential correction
techniques, but used higher PDOP masks (e.
In addition, the receiver may utilize an external source of differential correction
in RTCM-104 format.
For example, GarNet can provide the differential correction
data that would allow GPS-enabled handsets to meet and exceed the location accuracy required under the E911 Phase II mandate.
The Pro XRS combines a state-of-the-art GPS receiver with a high performance MSK beacon differential correction
receiver and a satellite differential receiver, all in a single compact package.
The inverse differential correction
technology developed by DCI complements our existing patented technology for integrating GPS, wireless data networks and the Internet," said Krish Panu, chairman and CEO for @Road.
The AgGPS 132, designed with The Choice(TM) technology, is a combined state-of-the-art GPS receiver with a high performance Coast Guard beacon differential correction
receiver and a satellite differential receiver, in a single compact package.
information and accuracy assist such as differential correction
The Pro XR's integrated real-time differential correction
capability not only provides submeter mapping accuracy, it also offers users precision guidance for locating new or previously visited sites.
The unit receives both the free GPS satellite signals and free differential correction
broadcasts from government- established navigation beacon reference stations in much of the world.
If your operation is outside of this coverage, alternative external sources of differential correction
can be connected (e.
Basic system operations consists of multiple differential correction
processors (DCP) that are synchronized by a fault-tolerant clock resident in each processor function.