direct-coupled FET logic

direct-coupled FET logic

[də′rekt ¦kəp·əld ¦ef¦ē¦tē ′läj·ik]
(electronics)
A logic gate configuration used with gallium arsenide field-effect transistors operating in the enhancement mode, whose low power consumption and circuit simplicity lead to high packing density and potential use in very large-scale integrated circuits. Abbreviated DCFL.
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This device operates at an equivalent speed of over 20 Gb/s using direct-coupled FET logic (DCFL) and super-buffer FET logic (SBFL) high-electron mobility transistor (HEMT) technology.

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