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finite state machine |
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See state machine.
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| SDL uses a finite state machine and describes the behavior in the form similar to a flow chart. Verifier automatically extracts properties from Verilog RTL designs to uncover such problems as multiple clock domain synchronization errors, Finite State Machine (FSM) deadlock, and Code Reachability errors. Both Saphirus and CMR Design Automation will sell the complete Solidify line, which includes the Solidify property checking engine, SolidAC[TM] for automated checking of common design issues such as clock domain crossing, dead code, finite state machine (FSM) deadlock and livelock, case statement pragmas, reset propagation, bus contention, X assignment propagation, and array out-of-bounds, and SolidPC[TM] for AMBA protocol verification. |
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