finite-state machine


Also found in: Dictionary, Wikipedia.

finite-state machine

[′fī‚nīt ‚stāt mə‚shēn]
(computer science)
An automaton that has a finite number of distinguishable internal configurations.
References in periodicals archive ?
Keywords: Application-layer DDoS attack, Path vulnerabilities-based attack, Web-resource-weighted-directed graph, Top M longest path algorithm, Finite-state machine
The finite-state machine (FSM) is used to model the dynamical processes for the state of the user's session and monitor the PVB attacks for the accurate detection of PVB attacks.
One of the novel contributions of this work is the treatment of the coverability graph of a PT-net as a finite-state machine, making model checking of the net states possible.
Model-checking algorithms traverse the finite-state machine of a Kripke structure and verify (or disprove) the truth of a particular temporal logic formula; this involves searching down appropriate combinations of paths (according to the meanings of the temporal operators in the formula) and checking the truth of the individual state assertions at each node along the way.
The embedded finite-state machines allow the user to implement customized motion-detection-based applications with a high level of flexibility, reducing the workload of the microprocessor by moving programming functionality inside the sensor.
For the example we selected for discussion, these are: development of techniques supporting heterogeneous modelling, including both formal "meta-models" and a software laboratory for experimenting with heterogeneous modelling; exploration of methods based on dataflow and process networks, discrete-event systems, synchronous/reactive languages, finite-state machines, and communicating sequential processes; making contributions ranging from fundamental semantics to synthesis of embedded software and custom hardware.
The software is also tightly integrated with Stateflow to model systems containing finite-state machines that may produce or be controlled by discrete events.
This tool generates bit-true, cycle-accurate Verilog and VHDL code from 80 standard blocks in Simulink and Signal Processing Blockset, as well as Mealy and Moore finite-state machines in Stateflow.

Full browser ?