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gate arrayA type of ASIC chip that is partially finished with rows of unconnected transistors and resistors. The chip is completed by designing and adhering the top metal layers that provide the interconnecting pathways to form logic gates (NAND, NOR, etc.). These final masking stages are less costly than designing a full custom chip from scratch, which requires a new photo-mask for every transistor and interconnection layer. Today, gate arrays are rarely used.
The gate array is made up of cells containing some number of transistors and resistors. Using a cell library (gates, registers, etc.) and a macro library (more complex functions), the customer designs the chip, and the vendor's software generates the interconnection masks. Quite often, many cells are never used and are essentially wasted. See ASIC, FPGA, PLD, hard macro and soft macro.
|Gate Array Cells|
|These are examples of basic cells. Bipolar transistors are used for higher output power.|