The dual core hard macro
implementations are the result of ARM's significant investment in advanced physical IP development in unison with processor and fabric IP technology, and leading-edge implementation flows from the EDA industry.
The integrated PHY and DLL, licensed as a hard macro
, reduces our integration effort and improves our time to market.
We are pleased to work with Tensilica and SMIC to develop hard macro
versions of the Diamond Standard processors," said Adam Kablanian, president and CEO, Virage Logic.
Our new Hard Macro
tool underscores QuickLogic's commitment to achieving this by providing a tool focused on maximizing efficiency and minimizing risk.
tw/), who specializes in comprehensive SoC design services, is licensing the LSI Logic ZSP400 hard macro
for use in its own multimedia platform, which will enable customers to design optimized audio/video SoC solutions.
NASDAQ: CEVA), the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, Brite Semiconductor (Shanghai) Corporation, a leading IC design and turnkey service provider, and Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI; SEHK: 981), today jointly announced a collaboration to provide hard macro
versions of CEVA's DSP cores for customers wishing to reduce the risk and design cycle time for their SoC projects.
The DDR multiPHY is a hard macro
similar to Synopsys' complementary DDR PHY offerings.
13um CMOS the CPU core is less than 1mm2 and the whole hard macro
integrating CPU, FPU, 32K D cache, 16K I cache, serial port, timers, real time clock, interrupt controller, bus interface and debug port is only 8.
Single port 10/100/1000BASE-T hard macro
for TSMC 40LP (VSC9905-01);
0 PHY, is designed to be delivered as a GDS II hard macro
, and is process technology proven and easy to integrate.
Open-Silicon optimized the hard macro
for a TSMC 40LP low-power process using ARM POP[sup.
As an additional way for customers to access the POP, ARM also offers hard macro
implementations for the 40nm G performance and power-optimized implementations, embedding the same optimizations contained in the Processor Optimization Pack.