instruction set architecture


Also found in: Acronyms.

instruction set architecture

(architecture)
(ISA) The parts of a processor's design that need to be understood in order to write assembly language, such as the machine language instructions and registers. Parts of the architecture that are left to the implementation, such as number of superscalar functional units, cache size and cycle speed, are not part of the ISA.

The definition of SPARC, for example, carefully distinguishes between an implementation and a specification.
References in periodicals archive ?
A valuable feature of this book is the use of ARC, a subset of the SPARC processor, for an instruction set architecture.
SMART NETWORKS DEVELOPER FORUM -- Underscoring its longstanding commitment to the PowerPC instruction set architecture, Freescale Semiconductor, a wholly owned subsidiary of Motorola, Inc.
org community, formed in 2005, is the collaborative, open organization driving innovation around Power Architecture[TM] technology through alignment of the instruction set architecture, development of standards and specifications, and nurturing of the Power Architecture brand.
These new CPUs are based on the ARMv6 instruction set architecture and are targeted at a wide range of deeply embedded storage, automotive networking and imaging applications such as high-performance disk drives, digital still cameras, engine management units and cable modems.
Thumb-2 core technology builds upon the existing ARM instruction set architecture, maintaining full compatibility with existing software investments and development toolchains.
SandCraft, founded in June 1996, develops and markets advanced superscalar microprocessors for high-performance networking equipment, office automation and high end consumer applications, based on the MIPS Instruction Set Architecture.
The Nios II family of embedded processors consists of three processor cores that implement a common instruction set architecture, each optimized for a specific price/performance point, and all supported by the same software tool chain.
Processors built on the new Power ISA will be software compatible at the user instruction set architecture level as with previous ISA versions.
Both products are based on the ARMv6 instruction set architecture.
The MPC5561 delivers an exceptional combination of high-performance computation and signal processing capabilities, while offering the reliability and familiarity of a proven instruction set architecture.
SandCraft develops and markets advanced superscalar microprocessors for high-performance networking equipment, laser printers and high end consumer applications, based on the MIPS Instruction Set Architecture.
This technology, which for the first time provides true instruction set architecture (ISA) independence, has tremendous potential to impact the entire computing industry, and its synergies with other emerging virtualization technologies are very exciting indeed.

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