internal bus

internal bus

A pathway between the CPU and memory. Contrast with external bus. See local bus.
References in periodicals archive ?
Lot 1: 2 external solid lines in broken lines as 4 external 1 internal bus lines (electric vehicle optional)
Summary: The Roads and Transport Authority (RTA) has inaugurated nine new internal bus routes in Dubai and one inter-city shuttle service between Dubai and Abu Dhabi.
Synaptics InterTouch is a high speed, low cost interface that utilizes an industry standard high bandwidth internal bus for true Multi-Touch "Full-Time Finger Tracking.
It has comprehensive diagnostic and logging functions to make testing and startup easier, and uses internal bus communications and plug-in modules for easier upgrades.
The cost of joining the mission is $2,800, including airfare from Miami, seven nights at Havana's Hotel Parque Central, one night in Miami, most meals, a guide and internal bus transportation.
The new NodalCore-X architecture has been improved to provide greater and more rapid extensibility with network downloadable custom hardware engines, coupled with a higher speed internal bus.
Output frequency of the Pierce oscillator is in internal MCU's PLL circuit increased to 32MHz resulting in internal bus clock frequency of 8MHz.
During the simulation, internal bus data can be displayed within System Studio in a transcript window or graphical; e.
Warwick University's student union is also attempting to bring back an internal bus service that was stopped a few years ago to travel around the site to prevent students having to walk home from campus bars at night.
In addition QuickLogic offers a variety of hot swappable PCI bridge ASSPs including 32-bit system master, bus master, bus target, and stand-alone target for 33 MHz and 50 MHz PCI busses, with internal bus speeds ranging from 33 MHz to 75 MHz.
USBLink Host will serve as the PicoBlue's internal bus and will connect Silicon Wave's Bluetooth Odyssey(TM) chipset with the T8302 ARM-based Phone-On-A- Chip(TM) IP Solution from Agere Systems.
has introduced the 3D-RAM5 (M2V40092DWG) integrated frame buffer memory architecture, the industry's first silicon combining DRAM and logic with a 1024-bit internal bus for 3D graphics.