interrupt handler


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interrupt handler

[′int·ə‚rəpt ‚hand·lər]
(computer science)
A section of a computer program or of the operating system that takes control when an interrupt is received and performs the operations required to service the interrupt.

interrupt handler

(software)
A routine which is executed when an interrupt occurs. Interrupt handlers typically deal with low-level events in the hardware of a computer system such as a character arriving at a serial port or a tick of a real-time clock. Special care is required when writing an interrupt handler to ensure that either the interrupt which triggered the handler's execution is masked out (inhibitted) until the handler exits, or the handler is re-entrant so that multiple concurrent invocations will not interfere with each other.

If interrupts are masked then the handler must execute as quickly as possible so that important events are not missed. This is often arranged by splitting the processing associated with the event into "upper" and "lower" halves. The lower part is the interrupt handler which masks out further interrupts as required, checks that the appropriate event has occurred (this may be necessary if several events share the same interrupt), services the interrupt, e.g. by reading a character from a UART and writing it to a queue, and re-enabling interrupts.

The upper half executes as part of a user process. It waits until the interrupt handler has run. Normally the operating system is responsible for reactivating a process which is waiting for some low-level event. It detects this by a shared flag or by inspecting a shared queue or by some other synchronisation mechanism. It is important that the upper and lower halves do not interfere if an interrupt occurs during the execution of upper half code. This is usually ensured by disabling interrupts during critical sections of code such as removing a character from a queue.
References in periodicals archive ?
As soon as a new byte is received by the serial communication interface, an associated receive interrupt handler is executed.
In addition, it is possible to attach a user supplied interrupt handler to a digital input.
Interrupt handler in the PS sets the flag for the host PC (see PCI Control Unit in Fig.
It exploits an untrusted pointer in the kernel with some help from a heap info leak, the ARM data abort interrupt handler and some techniques by Tarjei Mandt by Mark Dowd.
But on the other hand, interrupt handler has small differences in delay, because when the interrupt occurs, microcontroller has to do always almost the same operations, does not matter what kind of operation was done before.
If one of those "disabled" interrupts occurs, the RT-microkernel records its occurrence and returns without executing the MINIX interrupt handler.
Actually, there are four elements that contribute to the overall delay between an interrupt and the time the associated application program starts to run: interrupt latency, interrupt handler duration, scheduler latency, and scheduling duration.
It is responsible for handling the PCI bus enumeration (the method of determining all of the devices present in the system upon boot up) and is the PCI bus default interrupt handler.
This shift typically causes cache and TLB misses in the wake of the entry and the exit from the interrupt handler, or the context switch, respectively.
This hardware/software platform could also be the basis for designing an interrupt handler that would establish a uniform sample rate at which inserted control code would be executed.
A risky method to allocate CPU to handling specific protocol process above the interrupt handler is Receive Packet Steering (RPS) ([14]).
By using hardware performance counters and randomizing the interval between samples, we are able to sample activity within essentially the entire system (except for our interrupt handler itself) and to avoid correlations with any other activity.