interrupt latency


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interrupt latency

The time it takes to service an interrupt. It becomes a critical factor when servicing real-time functions such as a communications line. See UART overrun.
References in periodicals archive ?
The CLC peripheral allows designers to create custom logic and interconnections specific to their application, reducing interrupt latency, saving code space and adding functionality.
These new MCUs introduce and expand the offering of Microchip s Core Independent Peripherals (CIP), which were designed to reduce interrupt latency, lower-power consumption and increase system efficiency, and safety, while minimizing design time and effort.
It offers advanced features that are optimised for MCU and real-time embedded applications, including reduced interrupt latency, flash acceleration, debug features including iFlowTrace and support for AHB Lite as the interconnect interface.
embOS supports all four interrupt levels and fully nested interrupts with zero interrupt latency.
Reduced interrupt latency and deterministic and low-overhead thread scheduling enables applications such as LTE L2 scheduling to run on top of Linux with maximum performance.
today announced the availability of the PIC32MZ 32-bit Embedded Connectivity (EC) Microcontroller Family from Microchip Technology, with a powerful 200MHz MIPS core rated at an unprecedented 330 DMIPS and an interrupt latency of only 10 cycles.
An event handling system supports events such as prioritized interrupts, non-maskable interrupt and internal exceptions with a maximum interrupt latency of 16 clock cycles.
The design of the kernel interrupt management has been significantly improved in order to meet very high requirements on interrupt latency in multicore use cases.
The use of high speed DDR3 memory allows for deep waveform storage and tolerates the interrupt latency associated with non-real time operating systems.
Benchmark measurements show that Enea LWRT has an average interrupt latency comparable to Linux with the PREEMPT_RT patch, but with a worst case latency almost half as low, and a throughput (netperf) almost twice as high.
An event handling system supports events such as prioritized interrupts, non- maskable interrupt and internal exceptions with a maximum interrupt latency of 16 clock cycles.