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linear address space

    0.04 sec.

linear address space

See flat address space.


linear address space - A memory addressing scheme used in processors where the whole memory can be accessed using a single address that fits in a single register or instruction. This contrasts with a segmented memory architecture, such as that used on the Intel 8086, where an address is given by an offset from a base address held in one of the "segment registers". Linear addressing greatly simplifies programming at the assembly language level but requires more instruction word bits to be allocated for an address.


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The HIF comprises a 16-bit interface bus and two SRAM banks, each with a 1-KB linear address space.
In addition, the C161U provides five 16-bit multi-mode timers, a 16-bit watchdog timer, 16 programmable priority-level interrupts, and up to 2M bytes of linear address space for data and code.
Other C163-24D features include: A 1k byte dual-port scratch pad SRAM; a bootstrap loader ROM; synchronous and asynchronous serial interfaces; 2 multi-functional general purpose timer units with a total of 5 timers; an 8-channel peripheral event controller; a programmable watchdog timer; a 16 priority level interrupt system; 5 programmable chip selects and 16Mbytes of linear address space.
 
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