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linear-sweep delay circuit |
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linear-sweep delay circuit [′lin·ē·ər ¦swēp di‚lā ‚sər·kət]
(electronics) A widely used form of linear time-delay circuit in which the input signal initiates action by a linear sawtooth generator, such as the bootstrap or Miller integrator, whose output is then compared with a calibrated direct-current reference voltage level. Want to thank TFD for its existence? Tell a friend about us, add a link to this page, add the site to iGoogle, or visit the webmaster's page for free fun content. |
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