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memory cycle |
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A series of operations that take place to read or write a byte of memory. For destructive memories, it includes the regeneration of the bits. |
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? Mentioned in | ? References in periodicals archive | |
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Its 7-stage pipeline alleviates cache memory cycle time bottleneck, while the system bus logic repartitioning reduces the amount of logic needing to run at the maximum CPU clock speed. The reference design is ideal for communications and network equipment such as switches and routers that require substantial amounts of memory off the FPGA as well as high bandwidth and no delays between many random and intermixed read and write memory cycles. This enables GuardIT to perform security validations at memory cycle speeds and to operate independently of the security server. |
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memory cycle