memory hierarchy


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memory hierarchy

[′mem·rē ′hī·ər‚är·kē]
(computer science)
A ranking of computer memory devices, with devices having the fastest access time at the top of the hierarchy, and devices with slower access times but larger capacity and lower cost at lower levels.

memory hierarchy

The levels of memory in a computer. From fastest to slowest speed, they are:

1. CPU registers
2. L1 cache
3. L2 cache
4. Main memory
5. Virtual memory
6. Disk
References in periodicals archive ?
This approach uniquely takes advantage of innovations and design choices such as memory hierarchy and pipeline configuration which can directly influence the throughput of computational operations.
Their topics include memory hierarchy for multicore and many-core processors, the Cilk and Cilk++ programming languages, efficient Aho-Corasick string matching on emerging multicore architectures, sorting on a graphics processing unit (GPU), evaluating multicore processors and accelerators for dense numerical computations, and backprojection algorithms for multicore and GPU architectures.
The Oracle Exadata X3 Database In-Memory Machine implements a mass memory hierarchy that automatically moves all active data into Flash and RAM memory, while keeping less active data on low-cost disks.
In addition, it offers a new layer of the memory hierarchy in servers that has key advantages -space, heat, performance and ruggedness among them.
The structure of a memory hierarchy, in our case the design work, is given in fig.
The reason for this is that sparse matrix products operate significantly below the CPU's peak performance due to the bottleneck of data transfer in the CPU memory hierarchy.
Future operating systems may eventually support a memory hierarchy that includes directly accessing non-volatile solid-state storage as memory and not as "storage" at all.
Papers from an October 2006 symposium are presented here in sections on high-performance applications, grid and cluster computing, processor microarchitecture, performance measurement and analysis, memory hierarchy architecture, reconfigurable systems and operating system support for specific applications, and parallel and distributed algorithms, architectures, and interconnection networks.
The memory hierarchy surrounding the instruction units will have to be polymorphic, too, so memory circuits can be converted from L2 cache to a FIFO unit, for instance, when switching from SMP server mode to DSP mode.
The areas they cover are elements of a basic architecture, programming model and operation, memory hierarchy, and parallelism and performance enhancement.
a mass memory hierarchy that is designed to automatically move all active data
A Comparative Study Regarding a Memory Hierarchy with the CDLR SPEC 2000 Simulator, Innovations and Information Sciences and Engineering, Proceedings of the CISSE'06, Springer, pp 369-372, University of Bridgeport, USA