multiplier-accumulator

multiplier-accumulator

A general-purpose floating point processor that multiplies and accumulates the results of the multiplication. Newer versions also perform division and square roots.
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Multiplier and adder unit of Multiplier-Accumulator (MAC) control unit is the main building block in high end processors such as DSP, FPGA's etc .
Single-cycle 16 x 16-bit parallel multiplier-accumulator (MAC)
A Review of Different Type of Multipliers and Multiplier-Accumulator Unit, International Journal of Emerging Trends and Technology in Computer Science, 2(4): 364-368.
Over 40 dynamically controlled operating modes are supported including: multiplier, multiplier-accumulator, multipler-adder/subtractor, tree input adder, barrel shifter, wide counters and comparators.
The LatticeECP-DSP(TM) family adds a best-in-class multiplier-accumulator engine to the optimized architecture of the LatticeEC to support the expanding use of DSP functionality.
With availability of up to 512 DSP slices operating at 500 MHz, each DSP slice supports 18-bit by 18-bit, two complement multipliers, and over 40 dynamically controlled operating modes including; multiplier, multiplier-accumulator, multiplier-adder/subtractor, three input adder, barrel shifter, wide bus multiplexers, or wide counters.
The MCF547x and MCF548x families of microprocessors, based on the advanced V4e ColdFire core, offer the highest level of integration and include features such as memory management unit (MMU), floating point unit (FPU), enhanced multiplier-accumulator unit (EMAC) and on-chip multiprocessing.
The FPU incorporates multiply-accumulate and difference-of-products instructions that are suitable for Fast Fourier Transform (FFT) butterfly computation, as well as DSP-function instructions for the built-in multiplier-accumulator.
The '461 and '115 patents specifically require that the device have two instruction decoders; -- The '646 patent requires that PLA structures be used for decoding critical bits of each program instruction word; -- The PC modifier, as described in the '115 and '265 patents, modify (among other things) the T-bit in the program counter; -- The current program status register, as described in the '563 patent, is a single structure and is distinct from the saved program status registers; -- The user mode, as described in the '493 patent, denies access to privileged resources, while the system mode (which must be a form of exception mode) must provide access to those resources; -- The '804 patent requires multiplier-accumulator "N-bit results" that are different from "2N-bit results".
Its key features include: Support for four 32x32-bit multiplier-accumulators (MACs) per cycle with 72-bit accumulators, more than double the performance of other audio DSPs for computationally intensive functions such as fast Fourier transform (FFT) and finite impulse response (FIR), Support for eight 32x16-bit MACs per cycle under specified conditions, Four very long instruction word (VLIW) slot architecture capable of issuing two 64-bit loads per cycle, Optional vector floating-point unit available, providing up to four single-precision IEEE floating-point MACs per cycle, Software compatible with the existing HiFi DSP family consisting of over 140 HiFi-optimized audio and voice codecs and audio enhancement software packages.
The TCSI Lode DSP Core is the first general purpose DSP that provides two multiplier-accumulators (MACs) that reduce power consumption by effectively cutting cycle times in half.
Among the 30+ IP functions added in this new release of the Millennium PLC Software are the following: adders, subtractors, comparators, incrementers, decrementers, multipliers, encoders, decoders, shift registers, counters, multiplier-accumulators, pipelined multipliers, dynamic up/down counters, and tree multipliers.