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netlist |
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netlistA list of logic gates and their interconnections which make up a circuit. See logic synthesis. How to thank TFD for its existence? Tell a friend about us, add a link to this page, add the site to iGoogle, or visit webmaster's page for free fun content. |
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SpiceCheck performs netlist debugging from syntax verification to circuit-aware static checking and allows integrated circuits (ICs) and systems on chip (SoCs) designers to perform global checks on traditionally difficult-to-find design issues. The 360 EC-FPGA solution verifies functional equivalence between the register transfer level (RTL) code and the post-synthesis FPGA netlist, as well as between the post-synthesis netlist and the post-place-and-route FPGA netlist. In the new flow, FishTail's constraint management product Refocus[TM] is used to generate an exhaustive list of all the paths in a gate-level netlist that are made false by the false-path definitions in a Synopsys Design Constraint (SDC) file. |
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