pad limited

pad limited

A semiconductor chip that cannot be shrunk any further, because there would not be enough room for the bonding pads used for interconnection on the outer perimeter of the die. Although bonding pads are getting smaller, having shrunk below 50 microns, area array packaging has obviated the pad limited problem. See area array package.
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The 51micron pad pitch allows significant reduction of die size even for high pin count conversions that are often pad limited.
The comprehensive XC018 Master Kit for use with Cadence technology includes the Process Design Kit (PDK) as well as a low-power digital core library and I/O libraries for core and pad limited designs.
The Company's latest solution extends the applicability of wire bonding to a much wider range of applications, including high I/O pad limited graphics and ASIC chips, which can now stay with cost effective wire bond BGAs as opposed to 3x higher cost flip chip packaging.
In order to provide optimum solutions for pad limited designs, the TC203 series is designed to use Toshiba high density, 62 um inner lead TAB bonding package technology.
For I/O intensive devices that may be pad limited at current pitches, moving to 150 micron pitch may provide a more than 250 percent increase in I/O density.