parity checking

An error detection technique that tests the integrity of digital data in memory or on disk. Parity checking adds an extra parity cell to each byte of memory and an extra parity bit to each byte transmitted. The value of the ninth bit (0 or 1) depends on the pattern of the byte's eight bits. Each time a byte is transferred or transmitted, the parity bit is tested by memory controller circuits on the motherboard.

"Even" parity systems make the parity bit 1 when an even number of 1 bits are in the byte. "Odd" parity makes it 1 when an odd number of 1 bits are present. Parity checking cannot detect the condition in which two data bits are in error, because they would cancel themselves. The parity bit would still be correct for that sequence of 0s and 1s. ECC is a much more robust memory checking system (see ECC memory).

There are 12% more memory cells in 9-bit parity chips than there are in 8-bit non-parity memory. To shave costs, many computers are built with non-parity memory. It is truly a miracle that the data in the hundreds of millions of non-parity computers in the world are maintained as perfectly as they are considering the trillions upon trillions of bits moved daily. See RAID and ECC memory.