The DADDA scheme is one of the parallel multiplier schemes that essentially minimize the number of adder stages required to perform the summation of

partial products.

Partial product reduction scheme of a multiplier and a fused multiply-add unit lias a diamond shape structure [10].

The proposed designs can be used in designing reversible multi-operand adders and

partial product reduction stages of reversible multipliers.

This could be achieved by unfolding the iterative multiplier and yielding a combinatorial circuit that consists of several

partial product generators together with several adders that operate in parallel.

Next add the

partial products that correspond to the powers of 2 to make 19.

Unlike prior proposed reversible multiplier circuits, our reversible squarer circuit has simplified in only two main stages and the

partial product reduction stage which used in prior reversible multiplier circuits has removed.

Each

partial product is recorded without reference to total place value as each factor down the right side is multiplied by each factor across the top of the lattice.

The remaining bits of these

partial products are carried over to the next

partial product for addition designated as C1 to C6.

Awards may be made both to vendors offering a full line of products and vendors offering a

partial product line.

By using an array of AND gates, the

partial product terms are formed.