pipeline burst cache


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Related to pipeline burst cache: PB Cache

Pipeline Burst Cache

(hardware, storage)
(PB Cache) A synchronous cache built from pipelined SRAM.

A cache in which reading or writing a new location takes multiple cycles but subsequent locations can be accessed in a single cycle. On Pentium systems in 1996, pipeline burst caches are frequently used as secondary caches. The first 8 bytes of data are transferred in 3 CPU cycles, and the next 3 8-byte pieces of data are transferred in one cycle each.

pipeline burst cache

A common type of static RAM chip used for memory caches. After the first byte is accessed, access to subsequent memory locations takes fewer machine cycles than with previous designs. See L2 cache and static RAM.
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