pipeline stall

pipeline stall

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L1 cache provides information with effectively no pipeline stalls but is relatively small, while L2 cache has much more storage space but also higher latency (which means lost efficiency as the CPU cores wait for data to arrive from L2 cache).
Improvements include improved prefetch efficiency to reduce instruction pipeline stalls, increased buffer size for each instruction, grouping of cache requests and native FP16 / INT16 support.
In addition to dispatching instructions, the dispatcher allocates rename buffers and coordinates pipeline stalls.

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