reset condition

reset condition

[′rē‚set kən‚dish·ən]
(electronics)
Condition of a flip-flop circuit in which the internal state of the flip-flop is reset to zero.
References in periodicals archive ?
Unfortunately, the NCO was free running after the chip was released from the reset condition.
The devices will hold a microprocessor, microcontroller or system chipset in reset until the supply reaches the specified in-tolerance condition; and then maintains the reset condition for a minimum of 250ms before releasing the reset outputs providing time for the power supply to completely stabilize.
When the system voltage is below the operating range, the system enters into a reset condition.
These elements can be used to compensate the offset by toggling the Set/Reset elements between set and reset conditions (***, 2002; Caruso, 2003).
SLEC is also able to take into account complex design schemes involving multiple clocks and intricate reset conditions.
It includes a comprehensive set of analyses focused on such areas as synchronous design, initial reset conditions, hierarchical design, asynchronous circuits, clocks, and much more.