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scan technology |
Also found in: Wikipedia | 0.01 sec. |
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scan technology A method for testing chips on the printed circuit board by building the chip with additional input and output pins that are used only for test purposes. Full scan methods test all the registers on the chip. Partial scan tests some of them, and boundary scan tests only the input/output cells. JTAG is the IEEE standard for boundary scan. See also scan rate.How to thank TFD for its existence? Tell a friend about us, add a link to this page, add the site to iGoogle, or visit webmaster's page for free fun content. |
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