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set-associative cache

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set-associative cache [′set ə‚sȯs·ē‚ād·iv ‚kash]
(computer science)
A cache memory in which incoming data are distributed in sequence to each of two to eight areas or sets, and is generally read out in the same manner, allowing each set to prepare for the next input/output operation.


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The four-way set-associative cache memory is divided into two 32 Kbyte areas, one for instructions and one for data.
The two-way set-associative caches are nonblocking and support cache line locking.
SH-4A: Top-end 32-bit CPU core with cache, RAM and FPU The SH7397's high-performance SH-4A CPU core has two separate 32-Kbyte, 4-way set-associative cache memories -- one for instructions and the other for data -- to improve the cache hit rate for higher throughput.
 
 
 
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