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speed buffering

    0.01 sec.
speed buffering
A technique that compensates for speed differences between input and output. Data are accepted into the buffer at high speed and transferred out at low speed, or vice versa.


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Dias, DSM Research; "High speed buffering process for compact loose tubes," M.
The 3200DX FPGA family is the industry's first to combine into a single device the register-intensive datapath functions of FPGAs, the control and decode commonly implemented in CPLDs, and fast dual-port SRAM typically used for high speed buffering.
 
 
 
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