Joint Test Action Group

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Joint Test Action Group

(architecture, body, electronics, integrated circuit, standards, testing)
(JTAG, or "IEEE Standard 1149.1") A standard specifying how to control and monitor the pins of compliant devices on a printed circuit board.

Each device has four JTAG control lines. There is a common reset (TRST) and clock (TCLK). The data line daisy chains one device's TDO pin to the TDI pin on the next device.

The protocol contains commands to read and set the values of the pins (and, optionally internal registers) of devices. This is called "boundary scanning". The protocol makes board testing easier as signals that are not visible at the board connector may be read and set.

The protocol also allows the testing of equipment, connected to the JTAG port, to identify components on the board (by reading the device identification register) and to control and monitor the device's outputs.

JTAG is not used during normal operation of a board.

JTAG Technologies B.V..

Boundary Scan/JTAG Technical Information - Xilinx, Inc..

Java API for Boundary Scan FAQs - Xilinx Inc..

JTAG Boundary-Scan Test Products - Corelis, Inc..

"Logic analyzers stamping out bugs at the cutting edge", EDN Access, 1997-04-10.

IEEE 1149.1 Device Architecture - Boundary-Scan Tutorial from ASSET InterTech, Inc..

"Application-Specific Integrated Circuits", Michael John Sebatian Smith, published Addison-Wesley - Design Automation Cafe.

Software Debug options on ASIC cores - Embedded Systems Programming Archive.

Designing for On-Board Programming Using the IEEE 1149.1.

Built-In Self-Test Using Boundary Scan by Texas Instruments - EDTN Network.
References in periodicals archive ?
The integrated solution enables IP providers to develop and validate computer-readable IEEE-compliant descriptions for Silicon Instruments, the IP blocks in an SoC that are accessible via IEEE 1149.
This is a new language for documenting the procedure of the new instructions introduced in this IEEE 1149.
7 standard, a new two-pin test and debug interface standard that supports half the number of pins of the IEEE 1149.
The new standard, scheduled for ratification in Q1 2009, reportedly supports half the number of pins of the IEEE 1149.
RunnerClick is used in the testing of devices, boards and systems compliant with IEEE Std 1149.
ChipVORX is an in-system technology that can configure and control chip embedded test, debug, and programming functions based on the IEEE 1149.
One of the most efficient test technologies for electronics is boundary scan (1) (IEEE 1149.
Since the BSDL Verification System does not require detailed knowledge of the IEEE Standard 1149.
The third LVDS product is the SCAN921260UJB, a single chipset that incorporates six 1:10 deserialisers with IEEE 1149.