PCI Express

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PCI Express

A high-speed hardware interface from Intel for connecting peripheral devices. PCI Express (PCIe) was introduced in 2002, and by the mid-2000s, motherboards had at least one PCIe slot for the graphics card. PCIe is also used for hard drives, SSDs, Wi-Fi and Ethernet. Introduced in 2002 as "Third Generation I/O" (3GIO), PCIe superseded both PCI and PCI-X.

Switched Architecture - Multiple Lanes
Rather than the shared bus of PCI, PCIe provides a switched architecture of up to 32 independent, serial "lanes" that can transfer in parallel, designated 1x to 32x. The switch backplane determines the total bandwidth, and cards and motherboards are compatible between versions.

Internal and External for Laptops
A mini version of PCIe was developed for laptops (see Mini PCI Express) and ExpressCard and Thunderbolt interfaces extend PCIe outside the computer (see external GPU). For PCIe/PCI comparisons, see PCI-SIG. See PCI, M.2, ExpressCard, Thunderbolt and PCI-X.

                Data TransferPCI Express      (Bytes/Sec)Version      1 Lane      16 Lanes

    1.0        250 MBps     4 GBps
    2.0        500 MBps     8 GBps
    3.0          1 GBps**  16 GBps**
    4.0          2 GBps**  32 GBps**
  ** = rounded


Different Size Slots
PCIe is not compatible with PCI or AGP. Slots are color coded on the motherboard.







Parallel Transfer in Serial Form
Each lane is an independent single-bit serial channel on the PCIe backplane.







A PCIe Motherboard
This Asus motherboard has three x16 PCIe slots for x16, x8 or x4 cards and four x1 slots. (Image courtesy of ASUStek Computer Inc.)







PCIe Replaced AGP for Graphics
The AGP slot gave way to an x16 PCIe slot for the graphics card. (Image courtesy of NVIDIA Corporation.)







PCIe on an M.2 Card
This is a 960GB PCIe SSD contained on an 80x20mm M.2 card. See M.2.
References in periodicals archive ?
This means that while PCI (as in PCI-X, -2X, and maybe--4X) will dominate the parallel bus in PCs and servers for years to come, HyperTransport (HT), Rapid I/O (RIO), and now 3GIO present a new set of internal bus and backplane options as they are released.
Second, don't count PCI down-and-out or discard 3GIO because it is so far away (2004).
"But their problem will be acceptance by the rest of the industry; the organization only has 41 member companies, and Intel has not put up the $25,000 that steering members must contribute." Cary notes that Intel virtually controls high-volume bus adoption, and the chip giant has been developing its own, next-generation bus, code-named 3GIO.