6T SRAM


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6T SRAM

(6 Transistor SRAM) See static RAM.
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Dasgupta, "6T SRAM cell analysis for DRV and read stability," Journal of Semiconductors, vol.
Vladimirescu et al., "Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization," in Proceedings of the Design Automation Test in Europe Conference & Exhibition, pp.
Caption: Figure 3: Butterfly curve to obtain the SNM of 6T SRAM cell in hold mode (a) at [V.sub.dd] = 1V (b) by varying [V.sub.dd].
The main parameters that should keep in mind while designing SRAM bit cells are bit cell area, speed, stability, power consumption and yield .Figure1 shows the schematic diagram of conventional 6T SRAM bit cell.
The 6T SRAM equivalent schematic diagram during read operation.
In order to find a solution for the conflicting read versus write operation design requirement in the 6T SRAM Cell, Schmitt Trigger principle is applied for the cross coupled inverter pair is shown the Figure 2.
Using MWTA, the calculated area for a 6T SRAM cell is 6 MWTAs (6 minimum width transistor areas).
As shown in Table 3, 8T, 9T, and 10T SRAM structures show more than 50% higher read SNM (RSNM) as compared to 6T SRAM structure whereas 7T SRAM structure shows no significant improvement in RSNM.
Hasan, "Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron," Microelectronics Journal, vol.
In this paper, the stability and power evaluation of a FinFET-based 6T SRAM cell in SPICE-direct current (DC) and transient analysis are explored.
The RSNM, WLWM, and leakage of the proposed SRAM cells (DTIG7Ta-DTIG7Tb) have been compared with the corresponding ones such as traditional 6T SRAM cell (SG6T), 8T SRAM cell with read-write separation (SG8T), and SRAM cells using regular IG FinFETs (IG6Ta-IG6Td), as shown in Figure 10.
Xiao et al., "Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed," in Proceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI, pp.