8b10b

8b10b

(8Bits10Bits) A transmission code created by IBM in the mid-1980s that adds two bits to every 8-bit byte of data. The extra bits ensure that the line is electrically balanced between 0s and 1s, which enables the receiving circuits to stay in sync at high speeds. Using two conversion tables, the low-order five bits of each byte are encoded as six bits, and the next three bits are encoded into four bits.
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The recently announced BusMod SAS/SATA Error Injector capabilities like generating link errors such as 8b10b and CRC mismatch, adding and removing DWORDS to a frame, and modifying frame contents are now also made available to SAS and SATA developers working in a Linux environment.
At the encoding layer, SAS uses 8b10b encoding to create transmission characters and primitives from bits.
A single 510A Unit accommodates all rates from 50 to over 2,500 Mbps, using any scrambled NRZ, PRBS, or 8B10B coding format.
In addition, the ON Semiconductor TTP device will offer a configurable 8B10B coding at communication speeds of 10 Mbit/s using RS-485 physical layer.
The 8b10b encoding enforces several bit transitions per 10 bits even during data transmission; clock drift is minimized by continuously tracking these transitions.
The new library of SERDES components available with ADS includes 8B10B encoders/decoders; 64B66B encoders and decoders with and without scrambling; non-adaptive and adaptive feed forward and decision feedback equalizers, using a wide variety of tap optimization algorithms; and a new digital signal source capable of producing a de-emphasis waveform with random and periodic jitter modulation and transition wave shaping.
The data bytes to be sent out will need to be scrambled, then converted, through an 8B10B encoder, from an 8-bit to a 10-bit data stream, which is then handed to the specialized physical interface hardware block, or PHY.
The IEEE-1394 Signal Integrity Test Seminar will cover both IEEE-1394-1995 data strobe and IEEE-1394b-2002 8b10b test methodologies with demonstrations.
To address multi-protocol support, the HSBI is developing specifications for 8B10B, SONET/SDH, and 64B66B encoding schemes, so that they may be carried over an HSBI link.
To address multi-protocol support, the HSBI will develop specifications for 8B10B, SONET/SDH, and 64B66B encoding schemes, so that they may be carried over an HSBI link.
The XMAC II chip is designed on leading edge CMOS process technology and includes a fully integrated half and full duplex Gigabit Ethernet MAC, physical layer 8B10B encoder and decoder functions, RMON management support and multiple media interfaces.
The XMAC II chip now supports both the 8B10B PCS fiber optic and GMII 8-bit externally encoded transceiver interfaces.