process technology

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process technology

The particular manufacturing method used to make silicon chips, which is measured by how small the transistor is. The driving force behind the design of integrated circuits is miniaturization, and process technology boils down to the never-ending goal of smaller. It means more computing power per square inch, and smallness enables the design of ultra-tiny chips that can be placed almost anywhere.

Feature Size Measured in Nanometers
The size of the features (the elements that make up the structures on a chip) are measured in nanometers. A 22 nm process technology refers to features 22 nm or 0.22 µm in size. Also called a "technology node" and "process node," early chips were measured in micrometers (see table below).

The Exact Measurements
Historically, the size referred to the length of the silicon channel between source and drain in field effect transistors (see FET). The sizes of other features are generally derived as a ratio of the channel length, where some may be larger and some smaller. For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the gate terminal may be only 50 nm.

From 1,000 Nanometers Down to 10
The feature size of the 486 chip in 1989 was 1,000 nanometers (one micron). By 2003, it was 90 nm. The size was reduced by slightly less than one millionth of a meter. What may seem like a minuscule reduction took thousands of man years and billions of dollars worth of R&D. In the table below, note the dramatic reductions early on.

Chips Are a Miracle of Miniaturization
To understand how tiny these feature sizes are, it would take six thousand of these elements laid side-by-side to equal the thickness of one human hair. See half-node and active area.

Half a Micron Is Huge
In a span of five years, the feature size on these AMD chips was reduced from .8 to .35 microns. Half a micron may seem insignificant, but not in the microminiature world of semiconductor manufacturing. As features get smaller, the chip runs cooler and faster. (Image courtesy of Advanced Micro Devices, Inc.)

Semiconductor Feature Sizes(approximate for all vendors)       Nanometers  MicrometersYear     (nm)        (µm)

 1957   120,000      120.0
 1963    30,000       30.0
 1971    10,000       10.0
 1974     6,000        6.0
 1976     3,000        3.0
 1982     1,500        1.5
 1985     1,300        1.3
 1989     1,000        1.0
 1993       600        0.6
 1996       350        0.35
 1998       250        0.25
 1999       180        0.18
 2001       130        0.13
 2003        90        0.09
 2005        65        0.065
 2008        45        0.045
 2010        32        0.032
 2012        22        0.022
 2014        14        0.014
 2017        10        0.010
  ??          7        0.007
  ??          5        0.005

 Method       1        0.001
References in periodicals archive ?
Engineering teams from the two companies have been working closely together to port the processor design to Fujitsu's CS100 90 nm complementary metal oxide semiconductor (CMOS) process, which features transistors with a 40 nm physical gate length.
SAXS measurements were performed at the Advanced Photon Source at Argonne National Laboratory on test arrays of lithographically prepared structures with dimensions spanning 90 nm to 300 nm with a precision on the order of 0.
Over the next few years, growth will be underpinned by the semiconductor production at the 90 nm node and below.
Currently, the industry uses 193-nanometer-wave-length laser radiation to make wires and other circuit parts as thin as 90 nm.
Built with the most advanced triple-oxide 90 nm process technology and the widest range of embedded IP blocks, the Virtex-4 family reduces power consumption by 50% compared to previous generation.
Barcelona intends to launch its first 90 nm product in the first half of 2003.
The 90 nm process includes up to nine layers of copper interconnect integrated with a low-k dielectric, Organo-Silicate Glass (OSG), that has a k (dielectric constant) of 2.
Designers of memory-intensive applications using SOI or 90 nm and finer geometries are encouraged to meet with ISi at DAC in San Francisco, July 24-27, booth 1913 in the South Hall of the Moscone Center.
It is employed in a wide range of critical front end silicon etch applications on 200 mm and 300 mm wafers for technology nodes from 90 nm to sub-65 nm.
From a marketing viewpoint, he confirmed existing market research that indicated a rapid transition from the existing 130nm and 90 nm geometry to the 65 nm and should dominate industry standard in CY2007.
This milestone advances the state of SerDes (Serialization/Deserialization) ASIC core design from today's mainstream 90 nm to 65 nm process technology.
StarCore optimized both the architecture and the implementation of the SC3000 family products, to be scalable to 1GHz+ operating frequencies in 90 nm high performance processes.