Address Strobe


Also found in: Acronyms.

Address Strobe

(storage)
(AS) One of the input signals of a memory device, especially semiconductor memory, which is asserted to tell the memory device that the address inputs are valid. Upon receiving this signal the selected memory device starts the memory access (read/write) indicated by its other inputs.

It may be driven directly by the processor or by a memory controller.
References in periodicals archive ?
25-micron CMOS process technology, Mitsubishi's JEDEC-standard 64-Mb DDR SDRAM supports column address strobe latencies (CL) as stringent as CL 1.
The device also supports column address strobe (CAS) latency 2 and 3 (CL2 and CL3) for high-performance applications.
The new 256-Mb and 128-Mb devices are targeted for the most stringent "2-2-2" goal for CL2 (Column Address Strobe Latency 2) performance, as described in Intel's PC SDRAM specification.