The architecture of SPIHT with arithmetic coder is suggested by Kai Liu, Evgeniy Belyaev and Jie Guo (2012).
Power analysis done on update blocks of arithmetic coder shows that power is 40mw when carry select adder (CSA) is used whereas it is 42 mw with existing system using carry look ahead adder.
VLSI architecture of arithmetic coder used in SPHIT.
One factor that helped arithmetic coding gain the popularity it enjoys today was the publication of source code for a multisymbol arithmetic coder by Witten et al.
In the remainder of this introduction we give a brief review of arithmetic coding, describe modeling in general, and word-based models in particular, and discuss the attributes that the arithmetic coder must embody if it is to be usefully coupled with a word-based model.
In an arithmetic coder the exact symbol probabilities are preserved, and so compression effectiveness is better, sometimes markedly so.
In detail, a statistics module used with an arithmetic coder must be able to report the cumulative frequency of all symbols earlier in the alphabet than a given symbol, and to record that this symbol has occurred one more time.
They also operate at between a half and a quarter of the speed of the adaptive arithmetic coder described here.
