boundary scan

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boundary scan

The use of scan registers to capture state from device input and output pins. IEEE Standard 1149.1-1990 describes the international standard implementation (sometimes called JTAG after the Joint Test Action Group which began the standardisation work).
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scan technology

A method for testing chips on the printed circuit board by building the chip with additional input and output pins that are used only for test purposes. Full scan methods test all the registers on the chip. Partial scan tests some of them, and boundary scan tests only the input/output cells. JTAG is the IEEE standard for boundary scan. See also scan rate.
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References in periodicals archive ?
XJTAG delivers a diverse range of boundary scan test solutions for clients across a wide range of industries, including aerospace, automotive, defence, medical, manufacturing, networking, and telecommunications.
Acculogic, for example, will likely highlight its line of boundary scan test tools--including the ScanNavigator integrated boundary scan test environment--which can be used throughout the product life cycle from design verification and validation and continuing into pilot production and manufacturing and onto field service and repair.
The TAP controller state diagram shows the sequence of any boundary scan test through the TAP controller, and applies to components that comply with IEEE 1149.1.
The boundary scan test technology present in the PCBA is to increase test coverage of the components' early manufacturing defects (shorts/opens); complex PCBAs with masked vias tend to have limited test access points.
Designed specifically for Teradyne by JTAG, the solution with an advanced boundary scan test option is for manufacturers using the company's TestStation and GR228X family of In-Circuit Test systems, it said and added that two implementations of Symphony are supported by this collaboration for highest production test flexibility.
(2.) Test needs the netlist for Boundary Scan Test purposes only (3.) If OBD++ is provided the gerber is not required.
Keysight Technologies announced in March that SSP has achieved significant boundary scan test capabilities using the Keysight x1149 boundary scan analyzer in a standalone configuration or integrated with the Keysight i3070ICT system.
* Boundary scan interconnect and buswire test: Boundary scan test for interconnect pins between boundary scan devices.
The cells are linked together such that the tests executed during a boundary scan test do not need to pass through the core logic of the IC.
Boundary scan requires the IC designer to dedicate four or five physical pins, 200 gates of silicon and write boundary scan test code for the IC.
The key is how to put a process in place in the PCBA production cycle to ensure the possibility of a non-working or unstable boundary scan test is minimized or completely eliminated during production testing.
Indeed, in-circuit test equipment makers consider boundary scan to be a complementary technology, and in fact, Chari at Agilent said, "Boundary scan test is a subset of ICT technology." Boundary scan, he noted, is available as part of an in-circuit system or independently.