XJTAG delivers a diverse range of
boundary scan test solutions for clients across a wide range of industries, including aerospace, automotive, defence, medical, manufacturing, networking, and telecommunications.
The key is how to put a process in place in the PCBA production cycle to ensure the possibility of a non-working or unstable
boundary scan test is minimized or completely eliminated during production testing.
Keysight Technologies announced in March that SSP has achieved significant
boundary scan test capabilities using the Keysight x1149 boundary scan analyzer in a standalone configuration or integrated with the Keysight i3070ICT system.
The TAP controller state diagram shows the sequence of any
boundary scan test through the TAP controller, and applies to components that comply with IEEE 1149.
The
boundary scan test technology present in the PCBA is to increase test coverage of the components' early manufacturing defects (shorts/opens); complex PCBAs with masked vias tend to have limited test access points.
The cells are linked together such that the tests executed during a
boundary scan test do not need to pass through the core logic of the IC.
Designed specifically for Teradyne by JTAG, the solution with an advanced
boundary scan test option is for manufacturers using the company's TestStation and GR228X family of In-Circuit Test systems, it said and added that two implementations of Symphony are supported by this collaboration for highest production test flexibility.
Boundary scan interconnect and buswire test:
Boundary scan test for interconnect pins between boundary scan devices.
Boundary scan requires the IC designer to dedicate four or five physical pins, 200 gates of silicon and write
boundary scan test code for the IC.
Below are the following IEEE standards and
boundary scan test system features that enable test engineers to recover manufacturing test (FIGURE 2):
