Buffer Stage

buffer stage

[′bəf·ər ‚stāj]
(electronics)
buffer amplifier
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.
The following article is from The Great Soviet Encyclopedia (1979). It might be outdated or ideologically biased.

Buffer Stage

 

a stage of an amplifier of a radio transmitter or receiver using an electron tube or transistor. It serves mainly to eliminate or diminish the effect (reaction) of the following stage (after the buffer stage) on the preceding stage (in general, to eliminate the effect of load variations on a highly stable signal source).

The Great Soviet Encyclopedia, 3rd Edition (1970-1979). © 2010 The Gale Group, Inc. All rights reserved.
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It simply includes a buffer stage, and turn-on and turn-off gate resistors.
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Ecliptek's MEMS clock oscillators contain a MEMS resonator, an oscillator stage, frequency-temperature compensation, a low noise phase-locked loop, and a tri-state output buffer stage. A 200-mm CMOS wafer fabrication process for reduced lot-to-lot MEMS resonator variation, industry standard QFN (quad flat no-lead) packaging, and a COL (chip on lead) assembly process improve reliability while reducing assembly costs.
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The dissolution rate from enteric-coated pellets was assessed according to USP 23 method A, page 1795 (apparatus 2, 100 rpm, 37 [degrees] C, acid stage: 750 ml of 0.1 N hydrochloric acid for 2 hours and buffer stage: add 250 ml of 0.20 M tribasic sodium phosphate and adjust to a pH of 6.8).
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It consists of a voltage-controlled quadrature power splitter, two differential amplifiers, two double-balanced mixers and a positive feedback buffer stage. The voltage-controlled quadrature power splitter splits the input signal into two equal amplitude signals that are 90 [degrees] out of phase.
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The process platform provides the following devices isolated by SeJTET, including LVN/PMOS ([V.sub.DD]: 3.3 V) for digital analogical application, MVN/PMOS ([V.sub.DD]: 5 V) as buffer stages to drive the gate of HV device, and VDNMOS/LDPMOS (VDD: 150 V).
Novel BCD process platform with integrated self-extracted JTE trench technology for EL drivers ICs

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