Leakage current of CMOS IC--[I.sub.stat] could be defined as a sum of leakage currents of each individual CMOS transistor
--[I.sub.leak] that is under the voltage supply
Toshiba has developed a fabrication process for HfSiON gate dielectric film for 65nm low power CMOS applications and confirmed its characteristic with an experimentally fabricated LSI with 50nm gate-length CMOS transistors
The leakage current in CMOS transistor
depends on various process parameters, the transistor size and the quiescent state of the circuit.
The input impedance ([Z.sub.in]) depends only on the transconductance ([g.sub.m]) of CMOS transistor
as shown in (1)
The shortcoming of the method is that it neglects the static power dissipation (due to subthreshold leakage in CMOS transistors
) and does not account for power dissipation caused by incomplete logic transitions (glitches).
(2014)employedthe techniqueof boosting the gate-drive voltage of CMOS transistors
in pseudo-differential delay cells through the use of quasi-floating gate (QFG) architecture.
The contact resistance and the subthreshold slope of a CNFET are analogous to those of CMOS transistors
. The CNFET current is measured in current per tube and can be increased by increasing the number of tubes, while a CMOS current drive is characteristically represented in current per unit device width (e.g., [micro]A/[micro]m) .
The schematic diagram of half adder using CMOS transistors
is shown in the Fig.
With their fabrication process they have been able to integrate on a single technology platform two levels of advanced CMOS transistors
on top of each other using different substrates that have been bonded at low temperature.
TFETs could achieve a 100-fold power reduction over complementary CMOS transistors
, so integrating TFETs with CMOS technology could improve low-power integrated circuits.