Use of the technique is quoted as translating into an 8 ns propagation delay for the PZ3032 device and a 6 ns delay for the related 5 V PZ5032 CPLD
. The XPLA architecture is described as providing efficient product-term allocation and sharing capability in order to maximise density with a minimum of speed degradation.
Encoder/decoder for the RNS Modified Correction codes with the three data blocks and the one check number is implemented on CPLD
Most designers agree that a CPLD
device must have embedded non-volatile memory to provide a single chip solution that boots quickly.
The XPLA3 architecture also offers the most clocking options of any CPLD
available to simplify the implementation of logic designs.
Cypress Semiconductor Corporation (NYSE:CY), San Jose, Calif., has complete programming support available on Genrad, Hewlett-Packard, and Teradyne automated test equipment (ATE) for its Ultra37000 family of complex programmable logic devices (CPLDs
This is quite convenient for reliable operation of the commonly used integral digital components, including Complex Programmable Logic Devices (CPLD
) applied for integral implementation of the control circuits.
To help engineers learn more about the CoolRunner II family, the kit provides a XC2C256 CPLD
mounted on an X-shaped board that includes I/O pins on small headers.
One way to reduce system power is to allow a low-power programmable logic device, such as a CPLD
, to manage these offloaded operations.
Corelis announced the availability of ScanExpress Programmer, a universal in-system programming (ISP) tool which supports programming of CPLD
, FPGA, serial EEPROMs and flash memory devices.