The ADU CPU module consists of a single CPU chip, a 256KB secondary cache, and an interface to the system bus.
We implemented this logic because we knew these modules would be used to debug CPU chips. Test access logic would help us determine the cause of a CPU chip malfunction, making it possible for us to introduce errors into the secondary cache to test the error detection and correction capabilities of the CPU chip.
Finally, a CPU chip data cache duplicate tag store (protected by parity) functions as an invalidation filter and selects between update and invalidation strategies.
The CPU chip is supplied with a clock that is not related to the system clock in frequency or phase.
The bidirectional data bus of the CPU chip is converted into the unidirectional data busses used by the rest of the CPU module by transparent cut-off latches.
On reads, logic in the CPU chip clock domain closes all the latches and sends a read request into the bus clock domain.
Logic in the CPU chip clock domain controls all latches.
In fact, the bus interface cannot detect if a cycle is in progress in the CPU chip's integrated cache controller.
To keep pace with our schedule, we arranged for most of the system to be debugged before the CPU chip arrived.
We resumed testing the CPU module after the CPU chip was installed.