cache coherency

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cache coherency

(storage)
(Or "cache consistency") /kash koh-heer'n-see/ The synchronisation of data in multiple caches such that reading a memory location via any cache will return the most recent data written to that location via any (other) cache.

Some parallel processors do not cache accesses to shared memory to avoid the issue of cache coherency. If caches are used with shared memory then some system is required to detect when data in one processor's cache should be discarded or replaced because another processor has updated that memory location. Several such schemes have been devised.
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cache coherency

Managing a cache so that data are not lost or overwritten. For example, when data are updated in a cache but not yet transferred to the target memory or disk, the chance of corruption is greater. Accomplished by well-designed algorithms that keep track of every read and write event, cache coherency is even more critical in symmetric multiprocessing (SMP) where memory is shared by multiple processors. See cache and SMP.
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References in periodicals archive ?
His topics include perspectives on parallel programming, parallel programming for linked data structures, memory hierarchy organization, basic cache coherence issues, memory consistency models, and interconnection network architecture.
In order to make cache to function properly, certain factors are needed to be considered at the design stage of the cache which includes: the fetch algorithm, the placement and replacement algorithms, line size, cache coherence, the behaviour of separate data and instruction caches and cache size.
(8) Fong Pong, Michel Dubois "Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models" HP Laboratories Palo Alto, February, 2000.
[6.] Heinrich M.: "The Performance And Scalability of Distributed Shared Memory Cache Coherence Protocols".
Cache coherence management based on data trend analysis in HA-DMDB system.
Controls access to the file system structure using a global lock manager, and manages cache coherence and locking.
The directory-based cache coherence protocol for the DASH multiprocessor.
Hence the accesses are treated as operations applied to a single object, and cache coherence traffic is generated to ensure that the changes made to a block by a store operation are seen by all processors caching the block.
Cache coherence has also become an important new architectural feature in SMPs and in SPPs, especially those offering distributed shared memory (DSM).