carry-save adder

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carry-save adder

[¦kar·ē ¦sāv ′ad·ər]
(computer science)
A device for the rapid addition of three operands; consists of a sequence of full adders, in which one of the operands is entered in the carry inputs, and the carry outputs, instead of feeding the carry inputs of the following full adders, form a second output word which is then added to the ordinary output in a two-operand adder to form the final sum.
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References in periodicals archive ?
The structure of carry save adder has a longest critical path delay in the stages.
The incrementation blocks are used to finding the sizes of the stages in the hybrid variable latency carry save adder structure.
The carry save adder has three inputs (A, B, C) and two outputs (Sum & Carry-out).
Finally, a carry save adder is used to add these three together and computing the resulting sum.
The results of carry save adder performs approximately achieved the delay and efficient.
The combination of carry save adder with parallel prefix adder should be achieved minimum delay.
The parametric analysis of carry save adder is performed in parallel operation.
The combination of carry save adder with parallel prefix adder has more advantages than other adders.
In this paper, Hybrid Variable Latency Carry Save Adder structure was proposed, that achieved a higher speed and lower energy consumption.