Chip Scale Packaging

Chip Scale Packaging

(hardware)
(CSP) A type of surface mount integrated circuit packaging that provides pre-speed-sorted, pre-tested and pre-packaged die without requiring special testing. An example is Motorola's Micro SMT packaging.

See also: chip-on-board, flip chip, multichip module, known good die, ball grid array.

["Chip scale packaging gains at SMI. (Surface Mount International)", Bernard Levine, Electronic News (1991), Sept 4, 1995 v41 n2081 p1(2)].
This article is provided by FOLDOC - Free Online Dictionary of Computing (foldoc.org)
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The product is in the form of chip scale packaging and is expected to be helpful for various backlighting applications worldwide.
According to STATS ChipPAC the new 197,000 sq ft building will be located next to its current factory in Yishun, Singapore and will enable the company to expand its manufacturing capabilities for advanced wafer level technologies including embedded Wafer Level Ball Grid Array (eWLB), Wafer Level Chip Scale Packaging (WLCSP), Integrated Passive Devices (IPD) and Through Silicon Via (TSV).
of Singapore, a globally leading provider of chip packaging and test services, yesterday inaugurated a facility at its Taiwan subsidiary to deal with 300mm wafer bump and wafer level chip scale packaging (WLCSP).
The SiI 9020 is the first discrete HDMI transmitter designed specifically for the mobile/portable market, with reduced power consumption and chip scale packaging to meet the demands of highly integrated digital cameras and camcorders.
Unitive opened a new Die Level Processing (DLP) facility in the United States representing the industry's most advanced turnkey chip scale packaging capability.
Furthermore, Flip Chip forms the basis of more aggressive miniaturization methods, such as three-dimensional chip scale packaging described later.
All image processors are in chip scale packaging. In 10,000 unit quantities, the LM9704 is priced at $9.10, the LM9702 is $6.50 and the LM9701 is $7.80.
It utilizes chip scale packaging technology to realize a frequency range of 1173 to 1943 MHz with a step size of 1000 kHz It offers a phase noise specification of--96 dBc at 10 kHz offset and -120 dBc at 100 kHz offset or, equivalently, a BMS phase error of 2.1' integrated over 100 Hz to 100 kHz.
Therefore, the strong demand for 65/55-nanometer and below wafer manufacturing has prompted testing and packaging companies to expand their capacity to fill orders from upstream manufacturers for wafer bumping, WLCSP (wafer level chip scale packaging) and mixed-signal integrated circuit and high-speed logic circuit testing.