Then single data input is labelled D, used in place of the "set" signal, and the inverter is used to produce the complementary "reset" input thereby forge a level-sensitive D-type flip-flop
from a level-sensitive RS-latch as now S = D and R = not D is shown in the Fig.6
D-type flip-flop is used for sampling; toggle flip-flop counts 0-1 passages of GARO.
This system, which contains post-processing, has n delay elements and n D-type flip-flops. System is found to be successful in NIST tests, and data rate is measured to be around 10 Mbit/s.
Balmain, "Fast-transient susceptibility of a D-type flip-flop," IEEE Trans.
 reported the radiated susceptibility of D-type flip-flops implemented in various CMOS and TTL logic technologies.
The D-type flip-flop
generates the data on its Q output pin as the effect of the signal edge on its CK-pin.
There's a handy pair of devices in the 74xx series, the '373 (octal transparent latch) and '374 (octal D-type flip-flop
) respectively, that took care of the address de-multiplexing.