Then single data input is labelled D, used in place of the "set" signal, and the inverter is used to produce the complementary "reset" input thereby forge a level-sensitive D-type flip-flop
from a level-sensitive RS-latch as now S = D and R = not D is shown in the Fig.
Balmain, "Fast-transient susceptibility of a D-type flip-flop," IEEE Trans.
8] reported the radiated susceptibility of D-type flip-flops implemented in various CMOS and TTL logic technologies.
The D-type flip-flop
generates the data on its Q output pin as the effect of the signal edge on its CK-pin.
Semtech's first wave of ECL Logic products also includes a 4-bit D-type flip-flop
- the SK10/100E131 - that can be clocked separately from other flip-flops and features differential outputs.
Advanced features include mapping of logic to Mercury device logic and I/O atoms, automatic inference of single, dual, and quad port RAMs/ROMs, support of D-type flip-flops
with either set or reset and optimization to Mercury device counters.