DPLL


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DPLL

Digital Phase-Locked Loop
References in periodicals archive ?
The strength of consistency achieved by the unit propagation rule is reflected in the DPLL performance in many problems.
there is a trade-off between the effort spent on consistency and that spent on subsequent DPLL search.
Hitless reference switching--if the reference the DPLL is locked to fails, the DPLL will lock to another available reference without phase disturbances at its output.
Holdover mode--the DPLL constantly calculates the average frequency of the locked reference.
Microsemi's ZL30343 SyncE and IEEE 1588 packet synchronizer, part of the ZL3034x family of DPLLs, which provide all required clock synthesis and network timing functions for a central timing card or line card in carrier grade network equipment.
With its multicycle phase detector, the T0 DPLL can direct-lock to a number of common telecom frequencies even in the presence of significant jitter and wander on the reference clock.
The integrated DPLL provides N*64KHz clock generation and eliminates the need for an external clock source.
Systematic SAT Solvers Although it was discovered many years ago, the DPLL algorithm (Davis, Logemann, and Loveland 1962) remains a central algorithm, and it can be summarized with a minimum of background.
Our extremely accurate signal path and DPLL architecture eliminate the trade-offs and complexity of previous solutions to provide superior images and improved video quality for high-resolution monitors, projectors and televisions.
Traditional transmitter back-end building blocks made available to Altera customers include pulse-shaping FIRs, a reference-tracking DPLL, resampling interpolators, and an up converter.
Our DPLLs eliminate the trade-offs and complexity of traditional analog PLL solutions to provide sharper images and improved video quality for high resolution monitors, projectors and televisions.