double data rate

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double data rate

[¦dəb·əl ′dad·ə ‚rāt]
(computer science)
A clocking technique that increases the transfer speeds of synchronous memories by using both the leading and trailing edges of the clock signal to transfer data, effectively doubling the transfer rate or bandwidth.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.


(Synchronous DRAM) The type of dynamic RAM memory chip in wide use since the mid-1990s. SDRAM divides the chip into two cell blocks and interleaves data between them. While a bit in one block is accessed, a bit in the other is prepared for access. See dynamic RAM.

DDR (Double Data Rate) Since 2000
DDR SDRAM doubled the data transfer rate by using both the rising and falling edges of the clock cycle, and more speed is achieved with each generation (see below).

Memory Channels
Motherboards may support one, two or four channels. More than one channel requires installing modules in a prescribed order (see image below). See GDDR.

        Clock    Transfer        DIMM        Speed      Rate         Module DDR    (MHz)     (MT/s)    (V)  Pins

 DDR5 1600-3200  3200-6400  1.1  288
 DDR4  800-1600  1600-3200  1.2  284
 DDR3  400-1200   800-2400  1.5  240
 DDR2  200-533    533-800   1.8  240
 DDR   100-200    200-400   2.5  184
 SDRAM  66-133     66-133   3.3  168

Matched Slots for Dual Channel
Dual-channel motherboards use color-coded sockets so that DDR memory modules are inserted in pairs. This motherboard supports two pairs of DIMM modules (see memory module).

DDR RAM Modules Are "Keyed"
This example shows the notching of three DDR generations. Modules and slots are "keyed" to prevent the wrong DDR version from being inserted. See memory module.

A Little Nostalgia
These 12 bits of magnetic core memory from the Whirlwind computer of the early 1950s take up about a quarter of a square inch. Today, that much space holds billions of bits. (Image courtesy of The MITRE Corporation Archives.)
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References in periodicals archive ?
Tous ces elements ont permis a notre pays a amorce une double transition.
This double transition is attributed to the granularity of these polycrystalline samples [25, 26], arising from the weak Josephson intergrain coupling.
That double transition has reportedly delayed talks between the two sides on financing.
Part Four turns finally to the claim, cited by both thinkers, that "God itself is dead." Chapter eight--crucial in every sense--discusses Hegelian theodicy and follows Il'in on the "double transition" whereby each moment loses yet finds itself in the other (Fackenheim's "ubergreifen").
"By expanding production of these better products for the national market, India could not only prevent a surge of new climate change pollution, it would also avoid the added expense of a double transition from one technology to another over time."
They also claim that it is a well recognised fact that the middle school system, which involves a double transition for pupils, leads to a dip in their performance.
March 01 2012 (TUR) -- Italian Foreign Minister Giulio Terzi and Swedish Foreign Minister Carl Bildt will visit Turkey to attend an international conference on "Double Transition: Economics and Politics across Europe and the Mediterranean" which will take place in Istanbul between March 2 and 4.
Williams makes a similar observation regarding the double transition in Hegel's discussion of quantity and quality.
Simply put, despite the similar nature of the federation leaders' attitudes with those of its membership, the rapid changes to the South African labour market (as a result of the double transition) raise new and more complex problems for the federation.
La double transition d'une commune Vietnamienne By FRANCOIS HOUTART.
The Ultra2320 supports advanced SCSI Ultra320 features, including both single transition and double transition data transfers, hardware cycle redundancy checking, domain validation, packetized SCSI and parallel protocol request.
Ultra3 SCSI has six new features in its specification, including Double Transition Clocking (DTC), Cyclic Redundancy Check (CRC), Domain Validation, Protection for Asynchronous Information Phase (AIP), Packetization, and Quick Arbitration and Selection (QAS).