error detection and correction

(redirected from Error correction codes)

error detection and correction

(algorithm, storage)
(EDAC, or "error checking and correction", ECC) A collection of methods to detect errors in transmitted or stored data and to correct them. This is done in many ways, all of them involving some form of coding. The simplest form of error detection is a single added parity bit or a cyclic redundancy check. Multiple parity bits can not only detect that an error has occurred, but also which bits have been inverted, and should therefore be re-inverted to restore the original data. The more extra bits are added, the greater the chance that multiple errors will be detectable and correctable.

Several codes can perform Single Error Correction, Double Error Detection (SECDEC). One of the most commonly used is the Hamming code.

At the other technological extreme, cuniform texts from about 1500 B.C. which recorded the dates when Venus was visible, were examined on the basis of contained redundancies (the dates of appearance and disappearance were suplemented by the length of time of visibility) and "the worst data set ever seen" by [Huber, Zurich] was corrected.

RAM which includes EDAC circuits is known as error correcting memory (ECM).

[Wakerly, "Error Detecting Codes", North Holland 1978].

[Hamming, "Coding and Information Theory", 2nd Ed, Prentice Hall 1986].
References in periodicals archive ?
In both areas, LDPC code is one of the most promising error correction codes.
They cover securing low-cost RFID systems, the case for dynamic RFID tag authentication, a practical RFID ownership transfer scheme, an efficient ultralightweight authentication protocol for RFID systems, faster CRT-RSA decryption towards RFID applications, finterprinting RFID tags using timing characteristics, security flaws in a recent ultralightweight RFID protocol, a semantic access control model for RFID-enabled supply chains, security in the Internet of Things, securing RFID-supported supply chains, migrating covert channels in RFID-enabled supply chains, and anonymous RFID yoking protocol using error correction codes.
Each page contains a Spare Area, whose bytes are typically used for Error Correction Codes, software flags or Bad Block identification.
PCI Express supports two levels of Error Correction Codes (ECC) checking for both Data Link Layer and Transaction Layer errors.
of Newcastle, Australia) introduces iterative error correction codes and their associated decoding algorithms, as well as their design, implementation, and analysis.
The spare bytes are typically used for Error Correction Codes, software flags, or Bad Block identification.
During the write process the controller receives data from the host authoring application and calculates Reed-Solomon error correction codes for the data before it is written to the media.
Glavieux (telecommunications, Ecole Nationale Superieure des Telecommuncations de Bretangne), along with Claude Berrou, developed a new family of error correction codes called "turbocodes" and also pioneered the principle of turbo equalization.
As bit errors increase as NAND flash memory scales below 2xnm process technology and transitions to 3-bit per cell architectures, traditional error correction codes such as BCH, RS and Hamming code will no longer be sufficient.
It evaluates the architecture, design and performance of a number of OFDM variations, discusses coded OFDM, and gives a detailed study of error correction codes for access networks, 100 Gb/s Ethernet and future optical networks.
At high codes rates, TPC error correction performance approaches closer to the theoretical Shannon Channel Capacity Limit than any other commercially available error correction codes.
The new 72Mbit devices transparently encode and store error correction codes with every write and then read, decode and, if necessary, correct bit errors using a fast ECC algorithm.
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